Simulation is invaluable when creating circuit designs for implementation within integrated circuits (ICs). Often, circuit designs are simulated at the schematic level. That is, circuit designs can be simulated prior to layout of the circuit design. This means that the circuit can be simulated with respect to functionality, timing, and other aspects purely from the schematic of the circuit design prior to determining where the various components of the circuit design will be located on the target IC.
As IC fabrication technology continues to improve and circuit components become smaller, parasitic effects once considered minor become more significant, particularly when estimating circuit performance during simulation. The role of these parasitic effects can be observed through a comparison of pre-layout simulation results, referred to as schematic simulation, of a circuit with post-layout simulation results of the same circuit. Post layout simulation of a circuit may show a decrease in circuit performance, as compared to schematic simulation, of approximately 20 percent for the same circuit. In some cases, the divergence grows to approximately 50 percent.
This difference in simulation results between schematic simulation and post-layout simulation makes predicting circuit performance at early stages of circuit design very difficult. It often becomes necessary to continually re-optimize a circuit at later stages of development to recover this loss in performance once the layout process begins. Re-optimization, however, can lengthen the design cycle of the circuit and add significant cost to the process.